event counter vhdl
here is the code written:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clock,reset,temp)
begin
if(clock='1' and clock'event)then
if (reset='1')then
temp <= temp+"0001";
else
temp <="0000";
end if;
end if;
count <= temp;
end process;
end Behavioral;
Heh simulation working,post translate sim working..
Added after 15 minutes:
Here is aynchronous attempt which i did problem once again with PAR simulation,here is the code....
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clock,reset,temp)
begin
if (reset='1')then
temp <="0000";
else if(clock='1' and clock'event)then
temp <= temp+"0001";
end if;
end if;
count <= temp;
end process;
end Behavioral;
Added after 56 minutes:
glitches observed in
temp_3_dxmux_1
/temp_3_dymux_2