Counter using FSM verilog

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Can explain in detail?

I didn't get your Question.
 

counter is it self a fsm i.e its next state value depend upon previous state value ... refer books like RP jain, moriss mano or aanand kumar . In synchronous circuit chapter u will see the state diagram.

Or plz Explain ur question

Thanks and Regards
Vir
 

I didn't Know more about it.please explain it more.
 

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