kingslayer
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Dear all,
suppose I want to increment a value at each clock-cycle in VHDL. I can do the following, in which I omitted initial and declarations:
I guess that the synthesis tool is able to recognize a counter, but I have a doubt: the counter value I want is 4-bits wide, thus it takes values up to 15 inclusive; during functional simulation (e.g., using NCSim from Cadence), the value of the counter gets correctly reset to 0 every 16 clock-cycles.
My question is: will this functionality be preserved in the final implementation? I mean, is the synthesis tool able to add any extra logic to recognize and manage overflow situations? Or should I put this logic explicitely in the design?
Thanks for your attention
Cheers
suppose I want to increment a value at each clock-cycle in VHDL. I can do the following, in which I omitted initial and declarations:
Code:
-- [...]
signal counter : std_logic_vector(3 downto 0);
-- [...]
COUNT_UP_PROCESS : process (clk_i,rst_i) is
begin
if rst_i='1' then
counter <= (others => '0');
else
if clk_i'event and clk_i='1' then
counter <= counter + 1;
end if;
end if;
end process COUNT_UP_PROCESS;I guess that the synthesis tool is able to recognize a counter, but I have a doubt: the counter value I want is 4-bits wide, thus it takes values up to 15 inclusive; during functional simulation (e.g., using NCSim from Cadence), the value of the counter gets correctly reset to 0 every 16 clock-cycles.
My question is: will this functionality be preserved in the final implementation? I mean, is the synthesis tool able to add any extra logic to recognize and manage overflow situations? Or should I put this logic explicitely in the design?
Thanks for your attention
Cheers