could you help me about this vhdl error

[minemercan]

I take this error after simulating this code: can't find a pinstub/port in the symbol, function prototype, or other construct 'test' that represents a design file that corresponds to pin XA2 in the file.

this is a 16 bit CSA simulator

Thank you for help
Mine

The code is Below :

--16 BIT CARRY SKIP ADDER----
LIBRARY ieee;
Use ieee.std_logic_1164.all;

entity CSA_FIXED_SIZE is
port ( X,Y:IN STD_LOGIC_VECTOR (15 downto 0); --girisler
C :IN STD_LOGIC; --C girisi
S: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Coutut STD_LOGIC); --C cikisi
end CSA_FIXED_SIZE;


architecture STRUCTURAL OF CSA_FIXED_SIZE IS

Component adder5
port (tempX,tempY:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tempC :IN STD_LOGIC;
tempSut STD_LOGIC_VECTOR(3 DOWNTO 0);
tempCout:OUT STD_LOGIC);
end component;

Component skip4
port(SCin,SCp:IN STD_LOGIC;
Sp:IN STD_LOGIC_VECTOR(3 downto 0);
SCout:OUT STD_LOGIC);
end component;

--Signal signalP:std_logic_vector(15 downto 0);
--signal signalC :std_logic_vector(3 downto 0);
--signal skipCout:std_logic_vector (2 downto 0);


begin

Test : adder5 port map (X(3 downto 0),Y(3 DOWNTO 0),C,S(3 DOWNTO 0),Cout);
-- RCA1: adder5 port map (X(3 DOWNTO 0),Y(3 DOWNTO 0),C,signalP(3 downto 0),signalC(0));
-- SKIP1:skip4 port map(C,signalC(0),signalP(3 downto 0),skipCout(0));
-- RCA2: adder5 port map(X(7 DOWNTO 4),Y(7 DOWNTO 4),skipCout(0),signalP(7 downto 4),signalC(1));
-- SKIP2:skip4 port map(skipCout(0),signalC(1),signalP(7 downto 4),skipCout(1));
-- RCA3: adder5 port map(X(11 DOWNTO 8),Y(11 DOWNTO 8),skipCout(1),signalP(11 downto 8),signalC(2));
-- SKIP3:skip4 port map(skipCout(1),signalC(2),signalP(11 downto 8),skipCout(2));
-- RCA4: adder5 port map(X(15 DOWNTO 12),Y(15 DOWNTO 12),skipCout(2),signalP(15 downto 12),signalC(3));
-- ss:skip4 port map(skipCout(2),signalC(3),signalP(15 downto 12),Cout); --skipOut(3)
END STRUCTURAL;


--------------------------------------------------------------------
----------------------------------------------------------------------

--4 BIT RIPLE CARRY BLOCK----
----------------------------
LIBRARY ieee;
Use ieee.std_logic_1164.all;

entity adder5 is
port (XA,YA :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Cin :IN STD_LOGIC;
SA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout :OUT STD_LOGIC);
end adder5;


architecture Structure OF adder5 Is
signal c1,c2,c3:STD_LOGIC;
Component fulladd
port (Cin1,x1,y1:IN STD_LOGIC;
s1,Cout1 :OUT STD_LOGIC);
end component;
begin
stage0:fulladd port map (Cin,XA(0),YA(0),SA(0),c1);
stage1:fulladd port map(c1,XA(1),YA(1),SA(1),c2);
stage2:fulladd port map(c2,XA(2),YA(2),SA(2),c3);
stage3:fulladd port map(Cin1=>c3,Cout1=>Cout,x1=>XA(3),y1=>YA(3),s1=>SA(3));

end Structure;

---1 BIT FULL ADDER BLOCK----
LIBRARY ieee;
Use ieee.std_logic_1164.all;
entity fulladd IS
port(Cin2,x2,y2 :IN STD_LOGIC;
s2,Cout2 :OUT STD_LOGIC);
end fulladd;

ARCHITECTURE LogicFunc OF fulladd IS
begin
s2<= x2 XOR y2 XOR Cin2;
Cout2<=(x2 AND y2) or (Cin2 AND x2) or (Cin2 AND y2);
end LogicFunc;

------------------------------------------
------------------------------------------

---4 BIT FULL SKIP BLOCK----
LIBRARY ieee;
USE ieee. std_logic_1164.all;

ENTITY skip4 IS
port(Cin,Cp:IN STD_LOGIC;
P:IN STD_LOGIC_VECTOR(3 downto 0);
Cout:OUT STD_LOGIC);
end skip4;
ARCHITECTURE davranissal OF skip4 IS
BEGIN
Cout<= Cp or (P(0) and P(1) and P(2) and P(3) and Cin);
END davranissal;