could u please anybody answer to my question

[jyothi.k.jntu]

Q.3: Imagine yourself as a test engineer at a leading semiconductor company. Your manager wants to reduce the SCAN test time for an integrated circuit, which has a single long scan chain, by a factor of 10. However, the designers are reluctant to add additional scan pins by implementing ten scan chains. What alternative techniques can you and the designers explore to reduce test time? Discuss some techniques that you can use to tradeoff fault coverage with the testing time

 

[sunilbudumuru]

sol1:
multiplex the functional pins for the purpose of scan

sol2:
scan compression technique.

however, test time directly relation with the length of scan chain.



sunil budumuru