Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Could somebody explain Analog IC Design Flow?

Status
Not open for further replies.

wizard

Member level 2
Joined
Mar 30, 2002
Messages
51
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Location
China Mainland
Activity points
353
+analog design flow

I have no knowledge about Analog IC design.

Could somebody explain Analog IC Design Flow?

How do Analog IC designers describe analog ICs?
Do they have some kind of analog hardware description
languages like VHDL or Verilog for digital IC??

What software they use in the phases in the flow?
 

coppervaporlaser

Member level 3
Joined
Jun 23, 2002
Messages
64
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
495
as short as possible:

capture --> analog/MS design (based on spice, ahdl,vhdl,spectreS,... models) --> simulation analog/MS/digital --> transfer to layout --> layouter uses automatical check processors for netlist and lvs checks --> most of the analog cells are routed manually, digital cells --> auto place & route --> final check --> fab
 

okguy

Full Member level 6
Joined
Mar 1, 2002
Messages
360
Helped
15
Reputation
30
Reaction score
9
Trophy points
1,298
Location
China
Activity points
2,645
Schematic : Cadence is the best on WkStation
Simulation : HSPICE/Spectre/ELDO for small blocks
(ampli, comparator,VCO, ...)
Toplevel of analog : HSIM/nanosim they are fast but not accurate

Layout is stil drawn manually (nearly each polygon is drawn, ...)
extensisve usage of copy/paste/hierarchy/ parameterized cells.

With mixed signal, the best is HSIM to check the function, but not the performance.

Okguy?
 

sunjimmy

Full Member level 2
Joined
Jan 10, 2003
Messages
129
Helped
9
Reputation
18
Reaction score
7
Trophy points
1,298
Activity points
1,027
The analog flow I know

Step1- Capture schematic
Step2- Simulation
Step3- Layout
Step4- DRC (Design Rule Check) & LVS(Layout vs. Schematic check)
Step5- Layout extraction for some R & C parameters
Step6- Back annotate the parameters extracted in Step5
for post-layout simulation

If step6 is failed, either return to step1 or step3 to start another iteration.


Hope it helps : )
 

srik

Advanced Member level 4
Joined
Feb 9, 2002
Messages
106
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
706
Re: Analog Design Flow

wizard said:
languages like VHDL or Verilog for digital IC??

?
I dont think so because analog designing is done at
voltage/current_level_of_abstraction , which requires lot
of manual tweaking. I dont know if we have a HDL for analog design.

Besides analog simulation is mathematical/computational intensive/lot of floating point arithmetic/so on,
HDL simlation is logical simulation
 

gemini

Junior Member level 3
Joined
Nov 2, 2001
Messages
31
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
117
There is VHDL-AMS can deal analog language description.And the model is limited.
 

msdnge

Junior Member level 2
Joined
Dec 12, 2001
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
108
Verilog-A is a good choice for Analog System design and simulation . And SMASH from dolphin is an excellent tool for mix-signal design.
 

Laplace

Advanced Member level 4
Joined
Feb 26, 2002
Messages
103
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
659
There is an Analog extension for Verilog HDL. But as far as I know, there is no synthsesis tool for it yet.
 

cswang

Junior Member level 3
Joined
May 31, 2001
Messages
31
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
158
gemini said:
There is VHDL-AMS can deal analog language description.And the model is limited.
I agree you ! Because analog model can only descript 1 ~ 3 order behavior , a lot of non-linear item is hard to model !
 

okguy

Full Member level 6
Joined
Mar 1, 2002
Messages
360
Helped
15
Reputation
30
Reaction score
9
Trophy points
1,298
Location
China
Activity points
2,645
But HSIM or StarSim can read DSPF files.
So a kind of parasitic extraction is possible.

OkGuy?
 

aaronhor

Junior Member level 2
Joined
Jul 20, 2006
Messages
23
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,283
Activity points
1,395
There is a equilvalent HDL entry in analog design, which is verilog-A. It can be used in spectre simulator to model analog blocks such as op-amp, comparator, etc. The detail analog design flow can be found at :

Analog Circuits ~ Circuit Design World
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top