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Could somebody explain Analog IC Design Flow?

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Mar 30, 2002
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+analog design flow

I have no knowledge about Analog IC design.

Could somebody explain Analog IC Design Flow?

How do Analog IC designers describe analog ICs?
Do they have some kind of analog hardware description
languages like VHDL or Verilog for digital IC??

What software they use in the phases in the flow?

as short as possible:

capture --> analog/MS design (based on spice, ahdl,vhdl,spectreS,... models) --> simulation analog/MS/digital --> transfer to layout --> layouter uses automatical check processors for netlist and lvs checks --> most of the analog cells are routed manually, digital cells --> auto place & route --> final check --> fab

Schematic : Cadence is the best on WkStation
Simulation : HSPICE/Spectre/ELDO for small blocks
(ampli, comparator,VCO, ...)
Toplevel of analog : HSIM/nanosim they are fast but not accurate

Layout is stil drawn manually (nearly each polygon is drawn, ...)
extensisve usage of copy/paste/hierarchy/ parameterized cells.

With mixed signal, the best is HSIM to check the function, but not the performance.


The analog flow I know

Step1- Capture schematic
Step2- Simulation
Step3- Layout
Step4- DRC (Design Rule Check) & LVS(Layout vs. Schematic check)
Step5- Layout extraction for some R & C parameters
Step6- Back annotate the parameters extracted in Step5
for post-layout simulation

If step6 is failed, either return to step1 or step3 to start another iteration.

Hope it helps : )

Re: Analog Design Flow

wizard said:
languages like VHDL or Verilog for digital IC??


I dont think so because analog designing is done at
voltage/current_level_of_abstraction , which requires lot
of manual tweaking. I dont know if we have a HDL for analog design.

Besides analog simulation is mathematical/computational intensive/lot of floating point arithmetic/so on,
HDL simlation is logical simulation

There is VHDL-AMS can deal analog language description.And the model is limited.

Verilog-A is a good choice for Analog System design and simulation . And SMASH from dolphin is an excellent tool for mix-signal design.

There is an Analog extension for Verilog HDL. But as far as I know, there is no synthsesis tool for it yet.

gemini said:
There is VHDL-AMS can deal analog language description.And the model is limited.
I agree you ! Because analog model can only descript 1 ~ 3 order behavior , a lot of non-linear item is hard to model !

But HSIM or StarSim can read DSPF files.
So a kind of parasitic extraction is possible.


There is a equilvalent HDL entry in analog design, which is verilog-A. It can be used in spectre simulator to model analog blocks such as op-amp, comparator, etc. The detail analog design flow can be found at :

**broken link removed**

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