could some one help in correcting this VHDL code

[revooridinesh]

could some one convert this non synthesizable VHDL code to synthesizable

hi
i am new to VHDL
i have written a code to convert real values to 3 bit but real values cannot be synthesizable so is there any way to convert below non-synthesizable to synthesizable ?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fpadc is
port (clk :in std_logic;
bit2,bit1,bit0: out bit);
end fpadc;

architecture Behavioral of fpadc is
type sinvalues is array (0 to 12) of real;
signal sine : sinvalues :=(16.21,31.04,45.54,58.24,67.2,74.12,77.32,77.44,74.24,67.02,58.48,45.36,31.12,16.45);
signal inst : real;
begin

process(clk)

variable i : integer := 0;
--variable mn : real := 0.00;
--signal i : integer range 0 to 30:=0;
begin
if(rising_edge(clk)) then
inst <= sine(i);
i :=i+1;
--mn := 0.00-inst;
if ((inst<0.10 and inst>=0.00 ) or (inst>-0.10 and inst<=0.00) ) then --or
bit2<='0';
bit1<='0';
bit0<='0';

elsif ((inst<1.00 and inst>=0.10 )or (inst>-1.00 and inst<=-0.10) ) then --
bit2<='0';
bit1<='0';
bit0<='1';
elsif ((inst<10.00 and inst>=1.00 )or (inst>10.00 and inst<=-1.00)) then --
bit2<='0';
bit1<='1';
bit0<='0';
elsif ((inst<100.00 and inst>=10.00 ) or (inst>-100.00 and inst<=-10.00)) then --
bit2<='0';
bit1<='1';
bit0<='1';
elsif ((inst<1000.00 and inst>=100.00 ) or (inst>-1000.00 and inst<=-100.00)) then --
bit2<='1';
bit1<='0';
bit0<='0';

end if;
if(i = 12) then
i := 0;
end if;
end if;
end process;
end Behavioral;




Thank You

 

[K-J]

Re: could some one convert this non synthesizable VHDL code to synthesizable

hi
i am new to VHDL
i have written a code to convert real values to 3 bit but real values cannot be synthesizable so is there any way to convert below non-synthesizable to synthesizable ?

You can use the fixed/floating point packages. These packages are synthesizable. http://www.eda.org/fphdl/

Kevin Jennings

 

[revooridinesh]

@KJ
thank you for reply
so we need to include those packages in the code and replace 'real ' data type by what ?

 

[K-J]

@KJ
thank you for reply
so we need to include those packages in the code and replace 'real ' data type by what ?

If you use the fixed point package, then reals will be replaced by sfixed (assuming them to be replacing positive and negative reals) or ufixed (if they are replacing positive reals). Precision is defined by how the signal is declared:

signal xyz: sfixed(11 downto -10) would define a fixed point number with 12 bits of precision (i.e. 11 downto 0) before the binary point and 10 bits of precision (-1 downto -10) to the right of the binary point.

You convert between reals and sfixed/ufixed via the 'to_sfixed' and 'to_real' functions.

The fixed point package is generally what is used when implementing algorithms involving 'floating point' calculations. But there is a separate package for true floating point as well. Floating point consumes more logic resources than fixed point. Download the package and review the user's guide, it is fairly straightforward. The clumsiest part of it can be the resizing operations.

Kevin Jennings