Could real numbers in Verilog could be synthesized?

[walkon]

If I want to write a Verilog module that include some computation with real numbers and fractional numbers such like 3.3*4.5 or 2.2/3.4

I know it will be okay with the simulation , but is it okay with the synthesis process?

And, the input/output port of Verilog HDL didn't support 'real' declaration, right?
the real computation must be converted into a n-bit reg or rounded to a integer to be export to another module, right?

Thanks.

 

[checkmate]

real numbers are not synthesizeable. You'll have to use fixed point representation.

 

[soccer]

only fixed point number computation circuits can be synthesised.

 

[lychee]

In Hardware level, U can just implement the the fixed point computation.

the float point computation should implemted in
software level.

 

[dBUGGER]

Hi,
Real numbers cannot be synthesized. You have to use fixed point multiplication which is in some standard format say 1.15 format.

It also depends upon how you are getting your input data. If that is in floating point with exponent and mantissa then you have to convert it to appropriate fixed point and do the operations.

Best Regards,