convolutional encoder output xilinx

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rameshrai

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Hello,

I am trying to use the convolutional encoder ip core in xilinx. Why is the output not showing?



the input is 1 bit and output is 2 bit

thanks
 

Presumed the IP is O.K., you might have forgotten to stimulate the reset input in your testbench.
 

hi

there is no reset signal
 

The Xilinx encoder core I know has a reset input.

But it's unclear which you are using, how it was generated and if it's configured correctly.
 
hi,

i checked again, the reset isn't there. i used the ip and simple instantiated it with the main design, created testbench for data input as shown but i wonder why the output is not showing any output

- - - Updated - - -

hi,

u r right there is reset called synchronous reset(SCLR) which even don't sound like reset from SCLR but more like clear though i knew there is almost always pin to reset

but do you think it's because of this?
 

In hardware CLEAR and RESET are pretty much synonymous.

A reset clears the hardware to a known predefined state.
 
right, clear and reset means the same, i should have noted this

thanks i will check this
 

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