kurapati
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Hi,
I am trying to develop a generic convolution filter in verilog.
The filter is of 3x3 dimension with each sample be represented by 8 bits.
In the above image, Filter data and image data are 1-bit data coming into the filter. Output is 8-bit convoluted value.
To start with, I would like some ideas on the following:
1. I am not sure what exactly it implies: "each sample be represented by 8 bits"
2. How to stream the filter value and image data into FPGA serially?
3. How many memory banks would I need so as not to disturb the original image?
Thanks,
Kurapati
I am trying to develop a generic convolution filter in verilog.
The filter is of 3x3 dimension with each sample be represented by 8 bits.
In the above image, Filter data and image data are 1-bit data coming into the filter. Output is 8-bit convoluted value.
To start with, I would like some ideas on the following:
1. I am not sure what exactly it implies: "each sample be represented by 8 bits"
2. How to stream the filter value and image data into FPGA serially?
3. How many memory banks would I need so as not to disturb the original image?
Thanks,
Kurapati