1) Wanted to know if convolution coding and turbo coding can be implemented in a sequence.
2) What is the effort required to bypass an generic convolution code implementation on an FPGA? My current scenario is that I want to choose during field usage, the data in both coded and uncoded form.
2) What is the effort required to bypass an generic convolution code implementation on an FPGA? My current scenario is that I want to choose during field usage, the data in both coded and uncoded form.
Could be as easy as a mux. Or if you need it to be a seamless switch, then it gets more complicated as you'll need to start the bypass on some boundary and then match the pipeline delay of the convolution code so you can switch the bypass in seamlessly.