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Converting verilog RTL to verilog NETLIST

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andrepandi

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ise verilog netlist

.

Do you know any way to create a Verilog-based NETLIST from a Verilog RTL code?

I want to use it for a Xilinx FPGA.
Actually, I have seen in Xilinx ISE that the "post-place&route simulation model generation" creates something similar to what I intend to do. But it is prepared (obviously) for simulation purposes, and therefore it is using simulation models of flip-flops and other components.

Basically, I'd like to have a verilog file that has only LUT-s, FF-s and other primitive instances.

Is there any way to generate such file from for example the .ngc netlist?
 

ljkong

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verilog netlist to edif

yes. you can get it.
after you synthesize your design, you can select the output file which can be edif or verilog or vhdl.
when or after place and routing, you can not get it.
you can get want you want in this way.
good luck.
 

dBUGGER

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create a netlist from rtl

Hi,
you do get a vhdl/verilog/edif file after synthesis but that will comprise of only primitives like FF, LUT MUX etc.. Based on the architecture of the target FPGA... But this is very dificult to interpret as there there will be thousands of interconnections...

Best Regards,
 

andrepandi

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edif to verilog

Hi ljkong, you are right. I don't want to have a post par netlist, just a post-synt or post-translate. But I haven't found any option in ISE 7.1 to change the output netlist type. Could you give me any hints?

Actually I don't really know in which phase does the XST apply the area constraints. Translate, map or just at par?

It is not a problem for me if the resulting netlist is dependent on a certain FPGA family, so the netlist can be after translate as well.
 

ljkong

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ise edif verilog

in fact, i do not use XST. i just use Precision RTL or Synplify. those SW have the outfile what you want. i am not sure whether XST has this function.
and XST is one rtl synthesizer, so area constraints is no use for it.
it processes your design on logic level.
in edif file , using LOC attribute to define the position of logic.

after synthesizing , you can get edif ,vhdl or verilog outfiles.
after translating, you just can get ngo or ngd outfiles which is special format from Xilinx. no one can read it.
after maping, you can get ncd files which is from xilinx.
after PR, xilinx supply one xdl file which can be read by designer. but it is so difficult to read it.

good luck.
 

    andrepandi

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anjali

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edif to verilog xilinx

hi andrepandi, you can change the output netlist type in ISE, by changing the properties of "PAR" stage.

in ISE, there is one step "PAR" while building the project.by right clicking the PAR tab, we can get the properties. there is one option " output netlist type" with the options edif,verilog,vhdl. by default edif will be there.

Added after 38 seconds:


hi andrepandi, you can change the output netlist type in ISE, by changing the properties of "PAR" stage.

in ISE, there is one step "PAR" while building the project.by right clicking the PAR tab, we can get the properties. there is one option " output netlist type" with the options edif,verilog,vhdl. by default edif will be there.
 

mc&fpga

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hi,
isthere any way to interpret the vhdl(synthesized code) netlist to rtl code?
 

andrepandi

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Hi ljkong,
Thx for the hints, I managed to create a verilog netlist with Synplify.
It works alright, I could import it in the ISE.
Thx.


mc&fpga,
I could get the ISE to interpret the netlist code easily.
 

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