converting verilog code to gate level design..

[shakeebh]

gtech verilog model

Hi all

I have a verilog design described in dataflow model and want to convert it into equivalent gate level description. Is there any tool that can automate the task? And will ModelSim be able to do it?

Thanks

 

[khaila]

gtech verilog

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Synthesizer.

 

[ankit12345]

ModelSim is simulator only.
It cannot convert to gate level description.

Use any synthesis tool for conerting

 

[ram]

Hi,

Synopsys has a tool design compiler. Following is a method to create gate level equivalent for There GTECH library.

--------------------------------------------------------------------------------------------
To create a netlist with gates that are technology independent, you should use
a generic library, such as the generic technology (GTECH) library that Design
Compiler uses. Then to avoid DesignWare components in the netlist, compile the
design with the GTECH library as the target library.

The following tool command language (Tcl) script will give you the result you
want: a netlist made out of generic library cells.

#####
set synthetic_library "dw_foundation.sldb"
set target_library " ..../U-2003.06-1/libraries/syn/gtech.db"; # Change here to your installation path
set link_library "* $target_library $synthetic_library"

read_verilog { all verilog files of the design }

compile

change_names -rule verilog

write -out design_name.gtech -hier -format verilog

------------------------------------------------------------------------------------------

If you are using any other synthesizer ....find procedure equivalent to the gievn above.

bye,
Ram

 

[shakeebh]

Thanks for the reply ram.

If the way I put it was not patent enough, I actually want a gate level description in verilog. I have a very long design in dataflow and behavioral model and it will be extremely cumbersome to convert it manually. However, I will really appreciate if you (or anyone) can clarify that your method works for my scenario as well..

Thanks in anticipation

 

[shakeebh]

OK I am struggling to make it work on Leonardo Spectrum. Unable to find gtech.db thing, I copied gtech.v from Synplicity's installation copied it to leonardo and after a few hit and try attempts reshaped the TCL commands u gave into an acceptable format to Leonardo.

The output verilog code is somewhat encouraging.. assign statements and level sensitive always blocks are aptly replaced by "or" and "and" modules. However, always blocks with edge triggering signals are still being unreduced (it puts some code of its own instead of original always block, however it's still with always blocks with edge triggering).

I will be extremely grateful if someone can give some pointers to libraries or commands that can make my goal... The synthesis tools at my disposal are leonardo spectrum and synplicty pro

thanks in anticipation

 

[optor]

I guess FPGA companys can offer the library you need. Try their websites.