Converting synthesizeable RTL to SystemC and VERIFYING it!

[randyest]

I made a nice chip that is effectively a frame buffer with two clock domains and a bunch of buffer space (kind of like a FIFO,) and some special fancy control features and interfaces.

My chip has bout 150 I/O pins, a lot of DRAM, and roughly 5 million gates of logic. It works very well and is very good for some certain niche applications. I have someone that wants to use it, but they insist on having a SystemC model first. I have very little experience with SystemC. I know the idea, but haven't made any. I do know C/C++ basically, but not in this context. I am looking for general advice:

1) How to convert a synthesizeable RTL design with multiple clock domains to SystemC with minimal effort / tweaking / checking / customizing on my part

-(1a) I found out about verilator https://www.veripool.org/wiki/verilator -- are there other tools like verilator that I should consider?

-(1b) Has anyone used verilator or other RTL-to-SystemC conversion tools? Did it work well? How much manual work? How good was the result?

2) How to VERIFY that the SystemC model matches the RTL model?

-(2a) is there such a thing as formal verification between RTL and SystemC?

-(2b) if so, what tools and how reliable are they?

-(2c) how confident can anyone be in a SystemC model? I know how to be sure 100% that RTL matches gate-level, but can I ever have that same level of confidence in a SystemC model? How?

3) I am considering hiring Synopsys to convert my RTL to systemC

-(3a) Has anyone else done this and been happy/sad/mad/glad with the results? What went well and what went wrong? What would you have done differently?

-(3b) Are there other companies that can do the conversion? Is there a big difference in quality? In cost? In time to complete?

Sorry for so many questions, but I'm trying to list all of my concerns and get as much info as you kind folks can provide. I would greatly appreciate any comments or ideas, and will be very generous with donation points to everyone who replies

 

[neifert]

Re: Converting synthesizeable RTL to SystemC and VERIFYING i

For a chip of this size and with more than a single clock domain you'll have difficulty getting a pure translation solution to work. Carbon Design Systems offers a tool however to do exactly what you are describing. Our Carbon Model Studio product (http://www.carbondesignsystems.com/Products/ModelStudio.aspx) compiles synthesizable RTL into a software object and automatically generates a SystemC wrapper to enable direct integration into any SystemC environment. We also create an RTL wrapper which enables this same design to plug into your existing testbench so you can execute all the same tests against the Carbon object that you ran with the original RTL. This same tool is being used today by 50+ design teams and for IP distribution for models of ARM, MIPS, Denali and others.
I'd be happy to discuss this solution with you and talk about how we can meet your needs. Feel free to PM me or contact me via email: bill@carbondesignsystems.com

 

[randyest]

Thanks for the reply. I'm a little confused though - you say it maybe hard to get a pure translation to work, but it sounds like your tool is a pure translation tool? Did I miss something.

If you wouldn't mind addressing my other questions I would be willing to review your answers and the consider direct communication / discussion about next steps.

Thanks!

 

[neifert]

Re: Converting synthesizeable RTL to SystemC and VERIFYING i

Reasonable enough. Carbon Model Studio is not a translator, it is a compiler. It reads in the entire design, analyzes all of the data dependencies and clock relationships and then optimizes all of these relationships to maximize execution performance. In many ways, it is like a synthesis tool but instead of synthesizing into gates it instead synthesizes into instructions. The object which it generates is a linkable software object with a C API. We then automatically create a wrapper for that to integrate into RTL, SystemC or other virtual platform environments.

To address your other questions directly:
To verify the accuracy of the SystemC object you can choose either simulation or formal verification. The only company to my knowledge who has a formal verification tool between RTL and SystemC is Calypto. Their tool doesn't work on the object my company creates because we optimize the design too heavily. We have chosen to instead use simulation and automatically create the wrappers necessary to plug the design back into your original testbench. Note that although we provide this capability most of our customers actually don't use it. We've been doing this for long enough that most of our customers trust our results and don't independently validate the results (think about it, you don't run VCS simulation on your design to verify that NC got it right, or visa versa) So, addressing your other question, in this case you CAN be confident that your SystemC model matches your RTL 100%.

You mention that you're considering hiring a company to manually translate the design. While this is certainly a possibility, anytime you insert manual steps into a process you expose yourself to the potential for errors. It's not a trivial process and it's easy to make a subtle remodeling change which injects errors which are extremely difficult to track down. It's also then difficult to account for any design changes and means that should your design evolve at all you need to modify the design in both the RTL and the SystemC. Using an automatic approach you maintain your RTL as the golden model and have an automatic path to get to SystemC anytime you want.

Carbon has been around for over 8 years now and we've worked with 100s of design teams to do exactly what you're looking to do. Please let me know if you have any other questions.