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it's impossible. in MATLAB7 you can to implement the filters on vhdl only. and you can to test your design on vhdl in MATLAB with the external tool (ModelSim or Aldec)
Impossible? What about this product : **broken link removed**
I have not tried though, but I am very interested. Does someone have more details on this?
You have also Xilinx's System Generator. Test algorithms in Matlab then
implement them in Xilinx FPGAs. I don't know if intermediate files are HDL or EDIF.
OK .. SIT DOWN PLEASE .. MATLAB IS A VERY SIMPLE SEQUENTIAL LANGUAGE AND VHDL IS A COMPLICATED (STRONGLY TYPED) PARALLEL LANGUAGE .SO WHATEVER CONVERTER FROM ONE TO THE OTHER HAS TO DEAL WITH THIS ASPECTS SO IS NOT REALLY A CONVERTER OR A TRANSLATOR BUT A SYNTHESIS TOOL .. IT TURNS OUT THAT ACCELCHIP IS A PRODUCT THAT ORIGINATED AS A MATLAB COMPILER IN A UNIVERSITY .
BUT IS NOT AS MAGIC AS IT MAY SEEM .THE REASON IS THAT MATLAB THE PRODUCT RELIES A LOT ON LIBRARIES NOT WRITTEN IN MATLAB LANGUAGE BUT IN C++ FOR THE SAKE OF SPEED .SO THERE IS NOT EVEN MATLAB CODE AVALAIBLE .ON EXAMPLE IS THE ftt() function . SO HOW TO CONVERT TO VHDL SOMETHING THAT IS NOT EVEN WRITTEN IN MATLAB. WELL IS JUST IMPLEMENT THE EQUIVALENT IN ACCELCHIP AS LIBRARIES .BUT .HOW TO IMPLEMENT ALL THE HUGE AMOUNT OF FUNCTIONS OF MATLAB ...WELL THIS WILL TAKE YEARS
SO IF YOU GO AND SEE THE ACCELCHIP LIBRARIES( SOLD SEPARATLY LOTS OF $$$) .YOU WILL SEE ALL THAT CAN BE DONE WITH MATLAB LANGAUGE SO FAR
I dont think that matlab to vhdl conversion is useful because the design methodolgy of VHDL is very tough and parallel.
Matlab is aimed for testing and simulation while VHDL is a a hardware descriptive language and it also depends how a particular synthesizer looks your vhdl code.
VHDL was not designed to be a just an electronic hardware description language ,the proof is that there not even the basic notion of register..Is mostly used nowdays as as a HARDWARE DESCRIPTION LANGUAGE .VHDL was designed to be a general purpose simulation language ..It is posible to simulate all kinds of systems .mechanical ,pneumatic ..but today is mostly used in electronic hardware .. but it was not conceived directly to do just that .
it is not suitable for hardware design using tools for matlab to vhdl.
although there is some tools to do it.
hardware design is completely different from arithmetic research.
I think there is some confusion between people.
work in Verilog and VHDL is very different and the key is the design methodology of hardware which requires great skill of desing models and digital logic and every data flow and register is costly.
-Regards
Hello dear friends, I am in a student project of building a conversion utility to perform code conversion from MATLAB to VHDL. I have so far figured out to make
from .mdl to .rtw by real time workshop and then from .rtw to C code by the target language compiler using the .tlc files.
But I don't know why the C code is not get compiled and executed by the 'mbuild' command. Any suggestion how to run a C code in MATLAB.
What are the conversion utilities available so far for this project? Have any reference they are doing it! Please don't refer the PDF thesis and all those theoretical things. I need a practical way out.
Are all the blocks in MATLAB convertible in VHDL ? I don't think so. What do you think?
Please refer me if any C to VHDL conversion utility are known to you.
Bye bye. I'll be grateful to get any valuable information or suggestion from you.
Well but this tool will only work for code conversion and in context of performance it may not be of any use because the basic Ideolgy behind the VHDL or VERILOG is not the coding logic but the Design logic, data flow, delays, etc. and if someone considers all these in MATLAB too then may be conversion will help but why will anyone do all this in his Matlab code..............
I have personally tried running a design in VHDL using ModalSim v5.x, and testing my design on Matlab on (1) a image processing project and (2) an audio processing project in the past.
I don't think there is yet a conversion tool from Matlab to VHDL that is readily available in the market. But I think there could be some in-house tools in some companies that does this.
I have heard of a way from old friends in the ASIC industry. What they did was actually modifying the C lang statements in your .c file and implement them in the Process statement in .vhd to maintain the sequential nature, not unless you want some concurrent statements which in fact doesn't happen in C.
Additional viewpoint
============
I am seeing biased judgement against VHDL. That's not a very ethical to make, especially in engineering practices.
First and foremost, VHDL and Verilog works with some abstraction levels in common, although VHDL targets more of the system level abstraction and Verilog more to the circuit level abstraction.
I need to highlight the fact that both VHDL and Verilog originated from the USA, although USA seems to prefer imparting Verilog whereas Europe prefers VHDL.
Take note that the IEEE Circuits and Systems Society has its mainstream beginning to change side from Verilog to VHDL in the recent years being the fact Verilog is very much detached from high-level support because system architecture is shifting towards CONVERGING high and low.
I have also seen IEEE members, who are hardcore Verilog, mainly from the USA, beginning to soften in the past years when VHDL is seeing importance from the developments made in Europe and Asia Far East, especially when it comes to development of EDA CAD tools, modelling tools, synthesis tools, high-level language capatibility etc. VHDL is perhaps the only HDL we use or know that can bridge the gap between low level circuit and high level languages.
So I guess it is time not to bring in personal judgement against VHDL, despite this is a long American tradition wherever I go. I always hear discriminating opinions when my friends and I go to conferences in the States. I know the Americans seem to dislike VHDL very much.
Well... Both VHDL and Verilog are languages to help us solve problems in engineering, not something for us to argue over. That's my opinion to uphold ethical engineering practices.
One thing to note. It is an established fact that VHDL is harder to master than Verilog, based on statistics made in engineering education. Many academic professors also told me that students learn Verilog better than VHDL. So don't complain about VHDL when you cannot master it. If so many engineers can handle VHDL, why can't you? You just need to spend more time to learn it well. Not blaming it.
Its possible to convert matlab code to Verilog or VHDL.
Actually you can design systems directly from Matlab. For that you have to use tools like System Generator for DSP or AccelDSP from Xilinx. System generator works with Simulink.
Its also possible to use HDL designs with MatLab. Thats too is done via System Generator & Simulink.
Xilinx is actually referring these tools for DSP implementations.
Never!!!
Domain of VHDL is in Digital Electronic but MATLAB m files heve very large usage almost in any field of science.So It is impossible to convert form m file to VHDL.
But Simulink have facilities to generate VHDL code for some application.In addition you can use Link for Modelsim® Toolbax to simulation VHDL code form MATLAB.
aslo MATLAB and Simulink have facilities for FPGA design.
At least three tools exist for the current time that can link Matlab models and HDL implementation. These are Xilinx System Generator (it was described above), Altera DSP Builde (altera.com) and Simulink HDL Coder (it is included iin the last versions of Matlab). Whole of them support m-functions with limited capabilities.
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