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Converting LVDS to CML

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gavin23

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Hello:

How would I convert LVDS to CML? I've already done a Google search and read appnotes from Maxim & TI about interface conversion (see attached).

My problem is none of the appnotes explain why they do what they do.

Both AC couple when going from CML to LVDS. However, the Maxim appnote has two 5k pull-downs on the receiver side an the TI appnote shows a 10k pull-up and 10k pull-down on the negative leg. I understand in both cases this is for biasing but how did they come up with the solutions and why pick one over the other?

I have a 3.3V CML Clock Buffer and my receiver is LVDS with integrated 100R termination. The receiver doesn't say anything about its internal biasing. Currently I just use 100nF AC coupling caps with no additional biasing on the receiver end.

Any further insight on converting CML to LVDS would be appreciated.

Thanks,
Gavin
 

Attachments

  • Maxim - Interface - LVDS, PECL, CML - AN291.pdf
    119.5 KB · Views: 86
  • TI - Interface - AC - LVPECL LVDS HST CML - scaa059c.pdf
    417.1 KB · Views: 73

AC coupling would be also my suggestions.

A CML clock buffer may possibly require a DC load path, that's something you should review in the specification of your buffer.

The LVDS standard is pretty clear about the required common mode voltage, also all LVDS receiver datasheets I'm aware of. They generally need a DC bias to 1.2 V after the coupling capacitors. Input currents are usually low, so a 1 to 10 k resistor level would be sufficient.
 

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