#### trunkpk

##### Newbie level 3

**[SOLVED] Convert std_logic_vector to natural**

Hi, i have two std_logic_vector of 5 bits, with these i do a std_logic_vector of 10 bits. I need to convert this 10 bits vector into a natural number, range 0 to 1024.

I want to do this, to introduce the natural number in a rom and obtain the output.

But i have a lot of problems...

This is the code:

Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; ENTITY conver is PORT ( a, b: IN std_logic_vector (4 DOWNTO 0) ); END conver; architecture con of conver is SIGNAL aux: std_logic_vector (9 DOWNTO 0); SIGNAL aux1: integer range 0 to 1024; BEGIN PROCESS(a, b) begin aux <= a & b; aux1 <= to_integer(unsigned(aux)); end process; end con;

But doesn't run, and other configurations neither, like conv_integer.

Any suggestion?

Thanks

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