There is this weird obsession with numeric_std that leads to devs being very vocal about std_logic_unsigned while being much less vocal about Verilog. Basically, if you are against std_logic_unsigned you should not even acknowledge Verilog as a HDL. You should be aggressively shaming all Verilog users for the same objective reasons you are so vocal about std_logic_unsigned. There are legitimate reasons to be against Verilog/std_logic_unsigned, but they basically never enter the argument.