PCIe specification tells that "splitting of Ports into multiple Links" is an optional rather than a required feature, so you would check first if your PCIe host does support it.
I thought you have been talking about the PCIe reset signal PERST# which can be just routed forward or buffered by simple CMOS buffers. PRSNT# is however a present signal for hot-plug detection, please review the PCIe card electromechanical specification. You'll probably short PRSNT1# and PRSNT2# to signal permanent presence.
What exactly does not work? Clock distribution or communication with the PCIe devices? How do you test it? Does your host support the optional port splitting feature at all?
What exactly does not work? Clock distribution or communication with the PCIe devices? How do you test it? Does your host support the optional port splitting feature at all?
Thank you for your response. I attached my schematic .please check it.
just clock 1 work correctly but clock 2 do not work.
while slot1 connect to line 0 and slot 2 connect to line1.
I test it with a pc while connect it to a card ethernet to this converter .
Thank you for your replay.
How can check if my mother board supports this feature( port splitting)?
are there any other mistakes in my schematic design ?