convert code from verilog to vhdl

[chenghaibo]

hi,everybody.
i need the follow code to be writen in vhdl.
//function:convert gray code to binary
module gray2bin (gray, bin);
parameter SIZE = 4;
input [SIZE-1:0] gray;
output [SIZE-1:0] bin;
reg [SIZE-1:0] bin;
integer i;
always @(gray) for (i=0;i<SIZE;i=i+1) bin = ^(gray >> i);
endmodule
//
i know the code's meanings in verilog ,but my project is in vhdl,so i have to convert it to vhdl.
problem is that i don't know how to deal with the >> operation in vhdl.
can anybody help me?

 

[tut]

VHDL93 includes built-in shift operators:

sll (shift left logical),
srl (shift right logical),
sla (shift left arithmetic),
sra (shift right arithmetic)

See http://www.acc-eda.com/vhdlref/refg...nd_operators/understanding_vhdl_operators.htm

SRL is what u require..

tut..

 

[chenghaibo]

but quartus compiler doesn't support srl !!
waiting for help.............

 

[tut]

Predefined SRL operator works with bit and bit vector data types ONLY
(assuming u've done no overloading )
Also its a VHDL 93 operator, so u've to instruct ur simulator to use VHDL 93
syntax..

As i havent used Quartus Tool, so i can't say about that..
But u can use this code for RIGHT SHIFTER

-- A GENERIC LOGICAL RIGHT SHIFT OPERATOR FUNCTION

FUNCTION shftr (n: std_logic_vector; cnt: integer) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(n'LENGTH-1 DOWNTO 0):= ( OTHERS => '0');
CONSTANT len : integer := n'LENGTH-1;
BEGIN
IF cnt <= len THEN
result(len-cnt downto 0) := n(len downto cnt);
END IF;
RETURN result;
END shftr;

 

[maxer]

why don't you just get x-hdl and use it for traslation??


maxer

 

[nand_gates]

Here is what ur looking for ......

library ieee;
use ieee.std_logic_1164.all;

entity gray2bin is
  
  generic (
    SIZE : integer := 4);

  port (
    gray : in  std_logic_vector(SIZE-1 downto 0);
    bin  : out std_logic_vector(SIZE-1 downto 0));

end gray2bin;

architecture behave of gray2bin is

begin  -- behave

process (gray)
  variable bin_tmp  : std_logic_vector(SIZE-1 downto 0);
  variable xor_tmp : std_logic;
begin  -- process
  for i in 0 to SIZE-1 loop
    xor_tmp := '0';
    for j in i to SIZE-1 loop
      xor_tmp := xor_tmp xor gray(j);
    end loop;  -- j
    bin_tmp(i) := xor_tmp;
  end loop;  -- i
  bin <= bin_tmp;
end process;

end behave;

Hope this helps