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Convert BRAM to DRAM for Virtex -7 FPGA

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velu.plg

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I am try to convert BRAM to DRAM[Using Corgen] for my timing analysis process.BRAM have ENB port but DRAM does not have the same port.But I_CE port is available in DRAM.Is this I_CE port have same impact as such ENB port in BRAM,if it is correct in the sense what we do for dual port BRAM to DRAM conversion because only single I_CE port is available in dual port DRAM.
 

Study the Xilinx spec.
 

Study the Xilinx spec.
I think it's important that the OP understand that a DRAM is much different memory technology than BRAM and will require an interface that can handle delays in reading data and can deal with pending reads and writes when things like refresh occur. So just using the Xilinx DRAM controller will still require changes in the previous BRAM interface as the reads/writes will not respond in the same clock cycle as the BRAM did.
 

I think it's important that the OP understand that a DRAM is much different memory technology than BRAM and will require an interface that can handle delays in reading data and can deal with pending reads and writes when things like refresh occur. So just using the Xilinx DRAM controller will still require changes in the previous BRAM interface as the reads/writes will not respond in the same clock cycle as the BRAM did.

Am trying to convert Single Port BRAM to DRAM, in this scenario only one port is available. So, here read/write operation happen at different clock edge only ?
 

Something is confusing...
Is it possible for you to mention the primitive name?

An FPGA will have BlockRAMs (BRAMs) and Distributed RAMs. For both of these you have CoreGen or IP Catalog to generate them for you. Both these RAMs can be single port or dual-port. Now what is it you want to do?

Or are you trying to convert a single-port BRAM to DDR RAM (this remains off chip)? In this it is approach it is advisable to take the help of the MIG IP.
 

Something is confusing...
Is it possible for you to mention the primitive name?

An FPGA will have BlockRAMs (BRAMs) and Distributed RAMs. For both of these you have CoreGen or IP Catalog to generate them for you. Both these RAMs can be single port or dual-port. Now what is it you want to do?

Or are you trying to convert a single-port BRAM to DDR RAM (this remains off chip)? In this it is approach it is advisable to take the help of the MIG IP.

yes your understanding is correct. i have use following ports in single port BRAM.
clka,dina,addra,enb,wea,douta.
when i try to generate DRAM version for the above BRAM using corgen, i need to enable the register input option because in non-register mode i_ce pin is not available which is equivalent to enb pin of BRAM. I have done the verification run with register input which is failed but same testcase using BRAM is passed. ?
 

Then try creating the wrapper logic yourself over the generated one. This could give you more flexibility in the signal mappings. You may register the i/p and/or o/p as per your use case. For logic conversion use combination logic. Then try with your test case.
 
Last edited:

velu.plg,

Do not call distributed RAM "DRAM". The acronym DRAM typically stands for Dynamic Random Access Memory. This is why acronyms should not be used unless they are ubiquitous e.g. LED, USB, CD, etc.

The closest match between the two types of memory is:
  • BRAM with no extra registering being done and the ENA/ENB turned off with setting for the Enable port type set to Always enabled.
  • With the Distributed RAM the input registers enabled, the output registers disabled, the input clock enable not selected, and the dual port address enabled, the qdpo_clk will be the read port clock and clk will be the write port clock. Note you can not create a true dual port but only a simple dual port in the distributed RAM so we have to assume that is how the BRAM is configured.
Without actually implementing both of these myself (and verifying) I think this should be the closest in compatibility, but you will still need to create a wrapper for the distributed RAM to match the BRAM ports.
 

velu.plg,

Do not call distributed RAM "DRAM". The acronym DRAM typically stands for Dynamic Random Access Memory. This is why acronyms should not be used unless they are ubiquitous e.g. LED, USB, CD, etc.

The closest match between the two types of memory is:
  • BRAM with no extra registering being done and the ENA/ENB turned off with setting for the Enable port type set to Always enabled.
  • With the Distributed RAM the input registers enabled, the output registers disabled, the input clock enable not selected, and the dual port address enabled, the qdpo_clk will be the read port clock and clk will be the write port clock. Note you can not create a true dual port but only a simple dual port in the distributed RAM so we have to assume that is how the BRAM is configured.
Without actually implementing both of these myself (and verifying) I think this should be the closest in compatibility, but you will still need to create a wrapper for the distributed RAM to match the BRAM ports.

Am talking about Single port distributed RAM. My BRAM version have ENA [always enabled] if i want to get this port [i_ce] in distributed RAM i need to enable the registered version of input.

Any other modification need to perform while converting SP BRAM to SP distributed RAM??
 

Any other modification need to perform while converting SP BRAM to SP distributed RAM??
I have never done such a work myself so I can't provide you point to point instructions. Just do whatever your logical sense (after reading both the specs) says regarding the port conversion and then verify the working in a test-bench! Then when you see problems you can always come back and post a new thread.

Take note of ads-ee's answer too:
Without actually implementing both of these myself (and verifying) I think this should be the closest in compatibility, but you will still need to create a wrapper for the distributed RAM to match the BRAM ports.
 

I have actually done this conversion when a design I was working on ran out of BRAM for FIFOs. I ended up creating a distributed RAM FIFO to initially substitute for some of the BRAMs, but later changed that to all of the FIFOs.

Basically doing this takes a lot of work and requires that you create a test bench that checks all possible read write full empty burst interleved etc conditions you can think of. I ran this with random conditions generated for a long time. There's nothing prohibiting you from doing the same thing with a single port RAM.
 

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