[SOLVED] conversion from std_logic_vector to integer in numeric_std get me an error

[qwerty_asdf]

I have use those imports:

library IEEE;
use IEEE.std_logic_1164.all;

This is my code:

signal i:std_logic_vector(address_length-1 downto 0);

signal k: integer range 0 to 100:=0;
...
k<=to_integer(unsigned(i));

and this is my error:

com-1136) Unknown identifier "to_integer".

2) this one also get me an error.

Code:

out_temp<=inp1(0)+inp1(1);

where inp1.out_temp are std_logic_vectors. This is my error:

No feasible entries for infix operator "+".
** Error: C:/Modeltech_pe_edu_10.1a/examples/landmark_1.vhd(49): Type error resolving infix expression "+" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.

Am I not allowed to add 2 std_logic_vectors or is something else?

 

[std_match]

To_unsigned is defined in numeric_std.
You forgot to tell that you want to use that library:

use ieee.numeric_std.all;

And yes, you are not allowed to add std_logic_vectors. You must tell the tools what the bits represent. With numeric_std, you can cast std_logic_vector to "unsigned" or "signed" and then do the addition.

If you want to do arithmetic stuff, it is often very convenient to use the types "unsigned" and "signed" directly, instead of std_logic_vector. You can so that for signals, variables and ports.

 

[qwerty_asdf]

Thanks. i tried it on my own. I thought that use IEEE.std_logic_1164.all; was enough.