I'm converting some codes from VHDL to Verilog, and I have some difficulties in:
for example in VHDL, we can write something like that:
d : in std_logic_vector; --unconstrained vector or ports
where the size of this vector is determined at instantiation by the width of the input signal connected to it...what's the similar form of this in Verilog, if any?
...
Also, if I'm using this vector in the architecture, I'll use signal'range since I don't know its width, what's the similar to it in Verilog, if any? d <= (d'range => '0');
AA Salma,
Try this free tool at http://www.ocean-logic.com/downloads.htm
In addition to this, any HDL compiler that compiles both languages can make conversion. Check your tool documentation.
BR,
Amr Ali.