Convergence issue in HSPICE for simple resistor model

[wang159]

I write a verilog-A script for a simple resistor. The resistor has several identical segments, the number of which is defined as a parameter. The script is as follows

`include "disciplines.vams"

module Rloop(n,p);
	parameter integer total= 9 from [1:100];
	electrical p,n;
	electrical [0:total] in;
	parameter real R=1;
	genvar index;

	analog begin
		for (index = 1; index <=total; index=index+1) begin
			if (index == 1) begin
				// first segment next to p contact
				I(p,in[0]) <+ V(p,in[0])/R;
				$strobe("p > 0");
			end

			if (index == total) begin
				// last segment next to n contact
				I(in[index],n) <+ V(in[index],n)/R;
				$strobe("%d > n", index);
			end

			I(in[index-1], in[index]) <+ V(in[index-1], in[index])/R;
			$strobe("%d > %d", index-1, index);
		end
	end
endmodule

The circuit script is

Resistor test example

.hdl rloop.va

Vin in 0 DC 0

X1 in2 0 Rloop
R1 in2 in 1e-1

.DC Vin 0 0.1 0.002
.print V(in) I(Vin)
.end

This resistor simulation works fine in SPECTRE, but it fails in HSPICE, citing a convergence issue. Any suggestions for making the code converge in HSPICE? Am I doing anything that is undesired in Verilog-A?

Thanks for the help!

 

[kemiyun]

Hey, I don't have much to say about the convergence issue but use "if, else if, else" in your code. Like verilog it's better to have else condition for every if.

Here's the little intuition I have about the convergence issue, consider all these statements in the for loop calculated in parallel. In the first step connection to 0 wouldn't be declared in this case for the statement outside of the conditional loop to use. Why don't you start from 0 and do if(==0) first connection, else if(==total) final connection, else incremental connections. But I'm not really experienced enough to comment about this.

Logically, I don't see the thing you're trying to model here. You're not even tapping into the nets in between, why not put a single resistor?

 

[wang159]

Hey, I don't have much to say about the convergence issue but use "if, else if, else" in your code. Like verilog it's better to have else condition for every if.

Here's the little intuition I have about the convergence issue, consider all these statements in the for loop calculated in parallel. In the first step connection to 0 wouldn't be declared in this case for the statement outside of the conditional loop to use. Why don't you start from 0 and do if(==0) first connection, else if(==total) final connection, else incremental connections. But I'm not really experienced enough to comment about this.

Logically, I don't see the thing you're trying to model here. You're not even tapping into the nets in between, why not put a single resistor?

Hi kemiyun,

Thanks for the comments. This simple resistor code is indeed odd looking. The reason the first index starts at 1 instead of 0 is to bypass a SPECTRE problem. I am trying to make this code working in both HSPICE and SPECTRE. It appears to me that SPECTRE uses a rather straightforward way of checking verilog-A code: it disregards the "if, else" statements and substitute the index to every cell inside the loop. This causes the [index-1] to become -1 if the first index starts at 0. Of course, this does not happen if SPECTRE takes the "if, else" statements into consideration.

I am trying to expand this simple resistor model into more complex circuit. More elements will replace the simple resistors inside each loop.

 

[kemiyun]

No it's not doing anything unexpected. It does that because the statement that has [index-1] is out of the conditional part. If you can put if, elseif, else conditions I don't think you'd have the problem you mentioned. But again I'm not even sure if this is the problem.

Also why not get rid of p and n and make it completely parametric? This way you can tap into the nodes in between very easily too by just making them output. Just make sure that you define the length of the output with `define , I know spectre doesn't take parameter as length of an output array.

Also you can serially connect things in schematic very easily too, if that's what you're going for. Check out number 9 here:
https://mixedsignal.wordpress.com/2011/03/13/top-ten-tips-on-schematic-entry-in-cadence/

But it is your choice of course, I just don't see why verilogA wouldn't converge in hspice.