A possible solution to use a shift register for flexible multiphase clock generation.
Use the driving signal of the first phase as the input of a shift-register .
In this way a delay is obtained equal to the length of the shift-register multiplied by the clock cycle. The total length of the shift-register is at most equal to resolution of the duty cycle, while each driving signal is extracted from the position obtained
Cx= (x-1) R/N
where:
x = the phase number from 1 to N,
N = the number of phases
R = the resolution of the duty cycle, which is equal to the range of the counter.
These delays are equivalent to the desired phase-shifting operation, see the diagram attached: