constranit of xilinx product? thanks.

[vvsvv]

I want to know how to add constraint to xilinx spartan2e product?
&
what is the exact meaning of the constraint?
&
what is the main benefit after we add some certain constraint to FPGA?
:?:
thank again!

 

[geconom]

Do you have a specific tool you are using? This may help the discussion.

 

[vvsvv]

I am using ISE6.1 ,
and I can not use its floordesign OR FPGA editer etc.
:-(

and can not edit .UCF file,
may u help me?
thank again!!

 

[hoangthanhtung]

I also use ISE 6.1 so I think constrain means that we fix the pin of FPGA for my design. If you do not make constrain file (*.ucf) the ISE 6.1 software can automatic to define input pin and out put pin for your design.

Thank

 

[echo47]

Constraints let you control a wide variety of design details. If you use HDL, you can enter constraints in your source code. You should read the Constraints Guide:
https://www.xilinx.com/support/sw_manuals/xilinx6/download/

 

[M!k]

I am using ISE6.1 ,
and I can not use its floordesign OR FPGA editer etc.
:-(

and can not edit .UCF file,
may u help me?
thank again!!

You can always edit the UCF-file by opening it in an editor (notepad). In former releases of ISE WebPack v4 & v5 the constraint editor (GUI) had some bugs and strange behaviour. So I prefered to edit the UCF-file manually and everything worked fine. I don't know if this was fixed in v6.

Mik

 

[panns]

Above ISE5.1, you should create a *.UCF file first, then you can edit it.

 

[yerics]

In ISE 6.1 you can edit pin-related constraint by using PACE(Pinout Area Constraints Editor)
I think it's an interesting tool maybe of some use.

on timing related constraint, you can add them in constraint editor

anyway,you can edit *.ucf by notepad as you wish