Constraning an asynchronous design

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Sure.
Yet the only signal that requires CDC attention is the SCLK that's arriving to the slave. I.E, although this bus isn't synchronous to the FPGA system clock - it still has properties inherent to the protocol that we can exploit.
 

If you can ignore all previous advice, then yes, all previous advice is what you wanted to hear.
 


I would double sample, because in one word I'm "paranoid".

Basically I don't trust anyone else's designs, because I'm the one they always call in to fix someone else's F*** *P. That usually means both ends are suspect. Like the time I found a problem with the design I was called in to fix where the transmit side was tri-stating the output of the data intermittently a half clock cycle early, synchronous with the capture edge of the clock on an interface like SPI that has 180 phase shift between clock and data.
 

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