Constraints to synchronize inputs in a combinatorial blocks

[broussea]

Hi,

I have a design consisting of a 32-bit multiplier, in which data is fed through two 32-bits 8-way muxes. Due to the long combinatorial path of the muxes, the bits are not coming in the multipliers at the same time after place and route. This causes a lot of switching in the multipliers, and consumes a lot of power.

I'd like to know if someone here can suggest a good way to tackle this problem. Is there any constraints that specifies that every bit of a vector must have its transition at the same time as the others on pins from a combinatorial module?

As for the tools, I'm using design compiler and soc encounter.

Thanks!

 

[pmat]

Re: Constraints to synchronize inputs in a combinatorial blo

Hi,
a lot of gates and nets of combinational logic may change value more than once
during every mutiplication. This is due to the different delays of gates, wires, etc.
Multipliers are of the worse such examples, as their signals may change tens of
times before settling down. This gets worse, if the multiplier inputs change value
with large timing intervals each other. There are a lot solutions for this problem.
You can pipeline more the design after the MUX and before the multiplier inputs.
An other solution would be to put some "guard" latches which will block transitions
from propagating through the logic unless a condition is true. Finally, you could
play with monotonic combinational logic, where every gate and wire may alternate
their value only once. However, a 2x area overhead should be payed...

Pavlos