Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

constraints for synthesis of ASIC

Status
Not open for further replies.

ASIC_int

Advanced Member level 4
Joined
May 14, 2011
Messages
118
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,234
What are optimization constraints in synthesis. Lost down some of them and their implications.
 

yadavvlsi

Advanced Member level 3
Joined
Nov 19, 2010
Messages
978
Helped
485
Reputation
968
Reaction score
454
Trophy points
1,343
Location
Bangalore, India
Activity points
6,991
There are three main constraints in ASIC synthesis Timing, Area and Power. All these has trade-offs. If you wants better timing you may require large area and power. If you require small area your performance will effected.
 

ASIC_int

Advanced Member level 4
Joined
May 14, 2011
Messages
118
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,234
yadavvlsi

It did not answer my questions. I asked to list down some of the optimization contraints which are not timing constraints and the use of this optimization contraints in synthesis. Sorry my question was not clear earlier.

Regards
 

yadavvlsi

Advanced Member level 3
Joined
Nov 19, 2010
Messages
978
Helped
485
Reputation
968
Reaction score
454
Trophy points
1,343
Location
Bangalore, India
Activity points
6,991
We apply constraints to achieve some design goal. It may be maximum chip area, power consumption or timing requirements. I think there are not other constraints required. Our main goals are to achieve timing, area and power requirement. If you wants to optimized your design further these are the only constraints. Area constraints limits the maximum standard cell area and power constraints limits maximum power.
 

ASIC_int

Advanced Member level 4
Joined
May 14, 2011
Messages
118
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,234
yadavvlsi

You did not reply,

How many years of exp do u have? Which city are u located in India? Hope u are an Indian
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top