Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
There are three main constraints in ASIC synthesis Timing, Area and Power. All these has trade-offs. If you wants better timing you may require large area and power. If you require small area your performance will effected.
It did not answer my questions. I asked to list down some of the optimization contraints which are not timing constraints and the use of this optimization contraints in synthesis. Sorry my question was not clear earlier.
We apply constraints to achieve some design goal. It may be maximum chip area, power consumption or timing requirements. I think there are not other constraints required. Our main goals are to achieve timing, area and power requirement. If you wants to optimized your design further these are the only constraints. Area constraints limits the maximum standard cell area and power constraints limits maximum power.