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Constraint on combination logic in DC

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Junior Member level 2
Jul 18, 2005
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set_output_delay in dc

Hi all,
I use Synopsys DC to compile my design, and in the design:
A is the input, B is a sequential logic output of it, and C is a combinational logic output of it.
In my constraint file, for sequential part, I set constraint like below:
create_clock -period 20 -waveform {0 10} [get_ports {clk}] -name clk
set_input_delay -clock clk 4.0 [get_ports {A}]
set_output_delay -clock clk 6.0 [get_ports {B}]
for combination part, I set as following:
set_max_delay 5.0 -from [get_ports {A}] -to [get_ports {C}]

My goal is for combination logic, it should take up to 9.0 ns(4.0 + 5.0 = 9.0) from A to C.

And as a result, the path from A to C takes 3.0 ns actually, so that meet my goal(4.0+3.0=7.0<9.0), but DC thinks it takes7.0ns(4.0+3.0=7.0) and gives a violation report(5.0-7.0= -2.0).

So how should I configure my constraint file to reach my goal?

Kind regards,

synopsys design compiler path constraint

You need to change you set_max_delay constraint to set_max_delay 9.0, since you mentioned that your goal for total allowable delay from A to C is 9.0. By giving a constraint "set_input_delay 4.." you are telling the tool that your input is delayed by 4ns. And since your set_max_delay is set to 5, the tool will only allow for a 1ns delay for the combo logic within the design from A to C. Hence the violation. When you say set_max_delay -from A -to C it includes both the input delay and the combo delay ( I think you have assumed that this constraint applies only to combo delay)



Well, I think your suggestion is right, setting constraint like that will not get any vioalation.


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