constrain on output when pad added

[chaofawu]

when using DC, if the pads are added to the design and set_dont_touch,is it still needed to set_load to the output pins??

 

[lostinxlation]

Without output loads, DC optimizes the output delay based on too pessimistic or too optimistic condition and you would have a trouble in timing closure after P&R.

 

[chaofawu]

but the output pin has been connected to the pad,so why need set_load?

 

[lostinxlation]

Pad delay depends on the output load.

 

[girishbabu123]

In case you dont know .. PAD means the I/O buffer , its like a buffer cell with
level shifters and esd protection circutery , used to connect the IC to o/P world.

PAD is often used to refer I/O buffer as well as a BOND PAD , BOND PAD is just a pieces of metal. IO BUffer is connected to bond pad and then bond wires connect bond pad to the lead frame or in simple words the package pins


Pad delays generally very high . Its is important define realistic loads on pads.
IF you dont get those values from the board designers/package designers , have a look at the data sheet of the I/O pad and that will give you a rough idea