Consideration about electromigration: instantaneous current vs average current

[PGPPG]

Hello, I'm Pangi.

I have a question whether the instantaneous current is more of a problem, or the dc(average) current is more of a problem in the electromigration problem.

I think I have seen in the pdk that the current limit for width of a wire is determined as the dc(average) current.

However, when I search the cause of electromigration, I found that the MTTF(mean time to failure) is related to the current density.

In the case of duty cycled operation, by what factor should I decide the line with?

Thank you.

 

[dick_freebird]

Unidirectional (on/off) current would be duty cycle
averaged against the DC limit for current density.

Reversing current tends to "rebuild" the trace, at
least partially. I have seen 2X the DC current used,
when this is truly balanced (directionally, and duty).

Very narrow pulses or one-time threats (like ESD
test) I have seen supported by data, and use, 10X
the DC current density.

If you want to go further then you'd be expected
to do the reliability testing to prove it out (a long
and expensive proposition which your management
will probably not support).

PDK rules often "boil down" current density into a
simple "mA/um" rule (relieving you of the need
to figure in things that the PDK may not tell, such
as minimum metal layer thickness and step
coverage and notching process characteristics),
and denying you the opportunity to check their
work - which my experience says, should always
be done for a new-to-you foundry and process.

Narrow-line width and wide-line width can be
expected to vary differently with side-etch and
with a declared maximum metal notch. Yet one
size fits all, according to the foundry?

It's easy for a reliability engineer to take short
cuts, use default activation energies, neglect
conductor temperature rise and never measure
it, etc. leading to way-overconservative rules
that make designers suffer. And foundries absolutely
do not want you checking their "golden" rules.

I once worked in a technology where some of
these errors resulted in Met2 current density rules
being less than half of industry norms while the rest
were roughly on par. Because the Met2 trace was
stressed 10X the current density of the others and
this was calculated (by me, nobody else bothered
to check) to have caused about 100C additional
temp rise in the conductor, but this true temp was
not used to fit the acceleration factor.

 

[timof]

In general, there several critical current densities for electromigration:

- Average
- RMS
- Peak

For signal nets, the current flow is mostly bi-directional, so RMS and/or peak current densities should be checked.
For power nets (depending on whether this is static or dynamic EM checks), it's

In modern technologies, the ME current densities rules may be very complex, with current values being dependent not only on temperature, but on metal line length and width.

ESD current density rules, as was already mentioned here, are 10-20x higher than EM rules (since ESD events are much shorter in time, HBM and especially CDM).

Sometimes, for bad layouts, even latchup tests can burn metals/vias, so current densities should be checked there as well (by injecting the current into the guard ring).

There are different kinds of EM rules violations.
One is some bad layout mistakes, with current desities exceeding the critical values significantly (let's say 50-10x or more) - this will lead to very fast chip failures.
Another one, is where current densities are higher than critical by less than ~2x - then the failure may happen very late in the product lifetime.

I have heard about some companies designing in such limited lifetime, to ensure consumers buy their products every so often.