In general, there several critical current densities for electromigration:
- Average
- RMS
- Peak
For signal nets, the current flow is mostly bi-directional, so RMS and/or peak current densities should be checked.
For power nets (depending on whether this is static or dynamic EM checks), it's
In modern technologies, the ME current densities rules may be very complex, with current values being dependent not only on temperature, but on metal line length and width.
ESD current density rules, as was already mentioned here, are 10-20x higher than EM rules (since ESD events are much shorter in time, HBM and especially CDM).
Sometimes, for bad layouts, even latchup tests can burn metals/vias, so current densities should be checked there as well (by injecting the current into the guard ring).
There are different kinds of EM rules violations.
One is some bad layout mistakes, with current desities exceeding the critical values significantly (let's say 50-10x or more) - this will lead to very fast chip failures.
Another one, is where current densities are higher than critical by less than ~2x - then the failure may happen very late in the product lifetime.
I have heard about some companies designing in such limited lifetime, to ensure consumers buy their products every so often.