Consider a 2:1 mux , what will output if sel is"x"

[abhineet22]

mux + select x

Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ?

 

[madhan_gopalan]

mux select x

Hi,

I donot think when you go put the code in FPGA there will be a state called "X". This will be considered either as '0' or '1' in FPGA and the corresponding action will be taken. But we cannot say whether FPGA will understand it as '0' or '1'.

Please correct me if I am wrong...

Bye,
S.Madhanagopalan

 

[nand_gates]

o/p of mux when select is x

F will be 'x' if any or both inputs are '1'
will be '0' if both the inputs are '0';

 

[jas_bakshi]

mux +select (sel) is x

Hi

Try using casex construct,as it can resolve the contention(x) input to ur system.

Regards

 

[spauls]

2 to 1 mux with unknown

you can also use //synopsys full case dir.

 

[zysmith]

2:1 mux sel is x

maybe it varied from simulation tool to simulation tool. optimistic or pessimistic

 

[shashi_reddy21]

2:1 mux, select is x

hi if select is x ,then the output should be x only

 

[JesseKing]

what will be output if mux sel is x

If you mean the simulation behavior, I think the result might have a strong relation with your rtl code.

such as
assign f=(sel == 1) a:b;
assign f=(sel == 0) b:a;

these two code will give two different result when 'sel' is x.

 

[haosg]

sel.is

in simulaiton, the output should be x.
of courst , there are no x state in real circuits.

 

[eeeraghu]

independent 2:1 mux

If both the inputs are 0's then the output is 0
If both the inputs are 1's then the output is 1
if both inputs are different then the output is X,

May be it depends on the simulation tool we use, dobt about this please clarify?

 

[manik_vivek_82]

Re: Consider a 2:1 mux , what will output if sel is"x&a

if sel=x,output is also x ..

 

[nand_gates]

Re: Consider a 2:1 mux , what will output if sel is"x&a

If both the inputs are 0's then the output is 0
If both the inputs are 1's then the output is 1
if both inputs are different then the output is X,

May be it depends on the simulation tool we use, dobt about this please clarify?

This is Simulator independent! If any simulator does not reproduce this behavior
means that that simulator has a serious bug!

 

[power-twq]

Re: Consider a 2:1 mux , what will output if sel is"x&q

The output will be up to DC's assumption.

Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ?

 

[girish_wabale]

Re: Consider a 2:1 mux , what will output if sel is"x&a

what means by x wheather unknown or high impedance state??


if select is unknown output is also unknown


for high impedence stage it depends on type of mux used refer manufacturers datasheet