connecting Zynq PS UART t o Wifi module CC3200

[Sunayana Chakradhar]

Hello All,

I have 2 questions.

1) I have a zynq zc 7020 processor. I need to utilize the UART0 of PS and connect it with my WIFI module CC3200. CC3200 is a 4 wired UART. I want to know whether this can be done on vivado? What is the procedure to do it. Should i connect the UART signals in the Zynq PS to the CC3200 by writing a HSDL code?

2) Can I generate a constraints file for the PS subsection by enabling the PS UART? Or is it only if I connect the AXI GPIO or some submodules that i can generate the constraints file?

 

[moh.haroun]

I think that it is enough to place a uart module in the Block design in addition to GPIO if needed. You do not need to make a constraint file because the BSP generated would include the hardware modules you are working with and the communication with the wifi module would be through the uart module as in any microcontroller.

 

[Sunayana Chakradhar]

So if i just enable UART0 with the modem signals is it enough? The constraint files for the PS peripherals is automatically generated and doesn't need us to generate it as we do it for the PL section designs.

As far as I know the AXI UART IP core is majorly for generating a UART on the PL. I need to connect UART0 to the wifi module. Please correct me if my understanding is wrong

 

[moh.haroun]

No that is not right. The AXI UART IP core is used to provide UART connection with external circuitry.

 

[Sunayana Chakradhar]

So do you mean to say that i have to connect the PS UART0 to AXI UART lite or AXI UART full to bring it outside and connect it to an external circuitry? I have a 4/5 wired UART and AXI UART lite nor AXI UART full does not support 4/ 5 wires. Do you suggest me to write a HDL code instead and convert it an IP to connect it with PS UART 0 of the PS? This might consume resources on the FPGA in turn.

 

[moh.haroun]

all what you need to do is to map the uart pins to external pins in vivado. uart pins are exported to PL so you should map them from PL to external with no VHDL code needed.

 

[Sunayana Chakradhar]

okay i will connect the UART pins of Zynq PS to uart pins on axi_uart_16550 ip core. only the pins that are required by me (RX, TX, CTS and RTS) will be connected. Remaining signals will be assigned to a constant '0'. This should suffice.

 

[Sunayana Chakradhar]

Hi, Just a small clarification I need. Xilinx mentions something like this.

http://forums.xilinx.com/t5/Welcome-Join/Enabling-zynq-PS-UARt/m-p/680172/highlight/false#M33966

Does it mean that enabling the UART in the PS would be sufficient? I dont have to use AXI UART block at all?