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[SOLVED] Connecting two FPGA's together

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catalin560

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The output pin of an FPGA with a 5V voltage is connected to the input pin of a second FPGA with a 3,3V voltage. What problems implies the connection of the two FPGA's and what is the cause of such problem? What is the solution to this problem?
 

Unless the 3.3V FPGA has 5V tolerant inputs (only a few FPGAs have this feature) the 5V will exceed the maximum input voltage of the 3.3V FPGA and the 3.3V FPGA input connected to the 5V FPGA will be damaged.

The solution is
a) don't do this use the same voltage for the I/O that interface between FPGAs (3.3V). Most FPGAs allow for different bank voltages.
b) use a level translator IC.
c) emulate an open-drain/collector driver by tri-stating the 5V FPGA output when a high output level is needed (i.e. only drive the output low. Then pullup the pin with an external resistor to 3.3V.
d) use a voltage divider.
 
your answer is great but it depends on an unspecified feature of the second FPGA, what if it does have a input tolerance of 5V? What about this case? Could some errors pop up or the two FPGA's would just synergize perfectly?
 

Hi,
it depends on an unspecified feature of the second FPGA
Why unspecified.

If the device is 5V tolerant, then it surely is specified in the datasheet.

And you can see the behaviour in the datasheet (s). So there is no "guessing" or "try and error".

Klaus
 

These 5V tolerant type FPGAs are mostly exist as end of life stock as they pretty much have all been discontinued. Xilinx Spartan II was one such 5V compatible part even though it was designed for 3.3V see this. Expect to pay a fortune for many of these old parts.

Here is another part that is somewhat more recent that has 5V tolerance.

If you can switch to a CPLD there are a few more choices and possibly being somewhat more modern choices too.

I don't advise doing any of this, I already made some better suggestions of how to handle this.

- - - Updated - - -

what if it does have a input tolerance of 5V? What about this case? Could some errors pop up or the two FPGA's would just synergize perfectly?
I should probably mention that using the 5V tolerant 3.3V device connected to that 5V TTL output will result in a zener of 3.6V (which is typically how the inputs are protected) to be conducting the entire time that the output level of the 5V device is above 3.6V. This means you will be burning power when the signal goes high. So if you plan on doing this make sure that the level which is predominately on the pin is a low level signal and not the 5V (high) output.
 

Hi,

I should probably mention that using the 5V tolerant 3.3V device connected to that 5V TTL output will result in a zener of 3.6V (which is typically how the inputs are protected) to be conducting the entire time that the output level of the 5V device is above 3.6V. This means you will be burning power when the signal goes high. So if you plan on doing this make sure that the level which is predominately on the pin is a low level signal and not the 5V (high) output.

Interesting. I never seen such devices. But I never did use 5V input tolerant FPGAs. More CPLDs and logic devices.
All the 5V input tolerant devices I've seen don't draw more than 1uA of input current when input voltage is 5V. They are not 3V7 limited.

Klaus
 

Interesting. I never seen such devices. But I never did use 5V input tolerant FPGAs. More CPLDs and logic devices.
All the 5V input tolerant devices I've seen don't draw more than 1uA of input current when input voltage is 5V. They are not 3V7 limited.

Klaus

Well I've almost always avoided using anything at the wrong voltage, but they definitely have some sort of clamping circuit on the inputs to avoid any of that 5V reaching the input transistor, but from what I've read the clamping for true 5V tolerant inputs they usually use zeners with other circuitry to handle ESD and likely your current limiting (maybe some series resistance?). I just think it's better to use a voltage translator or pseudo-open-drain/collector outputs if you must connect a 5V output directly to a 3.3V input (which I've only had to do a couple of times ever).

The last time I ran into this problem we ended up using a small cheap FPGA to translate between 3.3V and 1.2V, which also allowed us to add some extra glue logic, which we also needed.
 

Someone pointed out that there could also be a problem about the buffer limit? I'm not sure what he meant... can someone explain?
 

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