sgergo
Junior Member level 1
Hi!
We have an analog oscillator with an emitter follower output, outputting 0...5V square wave with the frequency of 5 MHz. We wanted to measure the frequency change with 1Hz< sample rate so we have implemented a MachXO based reciprocal frequency counter in Verilog. We tested the frequency counter with a 6MHz TCXO and it was working great. However, when we connected our analog oscillator to the CPLD's signal input pin we experienced +/-100 Hz jitter in the measured frequency and additional 100Hz< spikes. We checked our analog oscillator with our frequency counter instrument which showed a stable output with no such jitter. We also checked it with an oscilloscope.
We suspected that the interfacing would be the problem, so we placed a 74HC132 quad NAND gate with Schmitt trigger input between the analog output and the CPLD pin. Now our readings were correct.
In the meantime another design flaw emerged as the CPLD pins maximum input voltage shouldn't be above 4.75V and we are feeding 5V into the inputs.
So the question is: how can we interface this 5V/5 MHz signal to the CPLDs CMOS input? Is there a logic chip (inverter, etc.) which can input 5V but outputs 3.3V?
Thank you in advance.
(attached a drawing for better explanation)
We have an analog oscillator with an emitter follower output, outputting 0...5V square wave with the frequency of 5 MHz. We wanted to measure the frequency change with 1Hz< sample rate so we have implemented a MachXO based reciprocal frequency counter in Verilog. We tested the frequency counter with a 6MHz TCXO and it was working great. However, when we connected our analog oscillator to the CPLD's signal input pin we experienced +/-100 Hz jitter in the measured frequency and additional 100Hz< spikes. We checked our analog oscillator with our frequency counter instrument which showed a stable output with no such jitter. We also checked it with an oscilloscope.
We suspected that the interfacing would be the problem, so we placed a 74HC132 quad NAND gate with Schmitt trigger input between the analog output and the CPLD pin. Now our readings were correct.
In the meantime another design flaw emerged as the CPLD pins maximum input voltage shouldn't be above 4.75V and we are feeding 5V into the inputs.
So the question is: how can we interface this 5V/5 MHz signal to the CPLDs CMOS input? Is there a logic chip (inverter, etc.) which can input 5V but outputs 3.3V?
Thank you in advance.
(attached a drawing for better explanation)
