Connecting Bulk and Source of an nmos for a non-RF applicati

[mhrnaik]

nmos bulk and source

Hello,

I am designing an amplifier which has to switch ON and OFF approximately 30 times per second. The amplifier is a folded cascode OPAMP with 2 gain boosting stages. When I run simulations, I get very good results for the bulk and source for all transistors connected together. Now I am drawing the layout of this amplifier.

As I understand, if there is an isolation layer of n-well b/w the substrate of the chip and the substrate (p-) layer of the nmos, I should be fine shorting these two conenctions together. Maybe I should use a deep n-well layer b/w the substrate of the chip and the nmos substrate?

If this is the case, can anyone tell me what purpose this isolation layer serves? Thanks.

 

[erikl]

nmos connecting

Maybe I should use a deep n-well layer b/w the substrate of the chip and the nmos substrate?

You can do this, if you like. But not necessary (and not recommended) for standard op. voltage transistors.

If this is the case, can anyone tell me what purpose this isolation layer serves? Thanks.

A deep n-well layer is a necessary prerequisite for HV nmos and pmos. Its layout, however, needs some more conditions, i.e. extended DRs, like longer-than-min. gate length, enough spacing between channel and drain contact, may be also between source and channel contact, and/or STI (isolation) between the channel and these contacts. See your PDK docu if such HV mosfet templates are available.

 

[dick_freebird]

Re: Connecting Bulk and Source of an nmos for a non-RF appli

Choice of where to tie the well can impact circuit AC
and DC performance. For example, a source follower
will have less capacitive load if you tie the well to the
negative supply, but also have a body-effect VT offset
(variable as well w/ common mode voltage); good for
AC, not so good for distortion and CMRR. The converse
is also true, you'll probably get better DC linearity with
body tied to source but a slower risetime etc. if the
device has to slap that big ol' well capacitance around.