Connecting a RAM cell to an I/O

[shaiko]

Hello,

Considering the fact that a RAM cell requires less transistors to implement then a DFF - why can't a RAM cell be used as a complete substitute to a DFF?

For example:
On FPGA's, I/O pins can be connected to a DFF...Is there a good reason why they can't be connected directly to a single bit RAM memory cell?

 

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The SRAM storage cell itself uses less transistors, but the access to it isn't anything like a DFF, no clock, no D, no Q. I'm sure it could be made to behave like a DFF but then it will probably end up with just as many transistors.

 

[shaiko]

I'm clearly missing something - this is how I see it:

"Access" can be divided into 2 types:

1. Read access - no such thing really. If the memory content is simply a voltage level, then we should be able to connect a wire to the point of storage and consider it being constantly and permanently read accessed. Just like connecting a wire to the Q pin of a DFF. Would you agree?

2. Write access.

process 
begin
  if rising_edge ( clock ) then 
    if write = '1' then
      Y<= X ;
    end if ;
  end if ;
end process ;

The above inffers RAM in Quartus. Almost the same behavioural description as a DFF (add an asynchronous reset and it becomes a DFF). Very similar "write access"...

What am I missing ?
Is #1 wrong?
Is #2 wrong?

 

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I'm pretty sure you're understanding of both #1 and #2 are incorrect.

You read an SRAM cell using a sense amplifier (we aren't talking about digital logic levels).

The inferred RAM in Quartus is because that is the way the tool interprets the code. It doesn't represent the way you have to inject (write) the value into the memory cell of an SRAM. An SRAM cell doesn't even require a clock, but Altera parts do require a clock to infer RAMs as there are DFFs built into the RAM to make the SRAM synchronous.

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You might want to look at this thread, a DFF doesn't require as many transistors as you think.

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Here is something really interesting posted on stack exchange on DFF designs. I especially found the three patents interesting.

 

[shaiko]

So...although RAM as a cell is more economical then a DFF it requires quite a bit of "service hardware" around it. This overhead becomes worthwhile only when the amount of memory is big - hence block RAM...

Then what is the purpose of Distributed RAM in FPGA?
If it also requires "service logic" but the price isn't shared among a lot of memory cells - why bother?

 

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Then what is the purpose of Distributed RAM in FPGA?
If it also requires "service logic" but the price isn't shared among a lot of memory cells - why bother?

Distributed RAM always exists as it's actually the configuration memory contents for a LUT. The logic to read the LUT memory already exists they just added the hooks into the write circuit to allow the fabric to write to the memory.