Bustigo
Member level 2
hello,
i have this problem
i want to communicate two xilinx fpga of type sparton 3E with 5 signals (wires)
the two boards have the same clock .. the communication between them through 1 data wire and its enable and 2 other data wires and their enable
how to synchronize 2 clocks without addition of bits
thank you
---------- Post added at 10:54 ---------- Previous post was at 09:21 ----------
another question
i have to detect this output
01010101(000000....00)10101010101
when having stream of zeros more than 4 i want output to be zero but the stream is anded with clock
i have this problem
i want to communicate two xilinx fpga of type sparton 3E with 5 signals (wires)
the two boards have the same clock .. the communication between them through 1 data wire and its enable and 2 other data wires and their enable
how to synchronize 2 clocks without addition of bits
thank you
---------- Post added at 10:54 ---------- Previous post was at 09:21 ----------
another question
i have to detect this output
01010101(000000....00)10101010101
when having stream of zeros more than 4 i want output to be zero but the stream is anded with clock