I have the following question for my fellow circuit enthusiasts..
It might seem like a very stupid question(it might be actually stupid)
I am confused with the following circuit.
It's a simple D flipflop. It's D input changes at the clock edge. What should be the output? Confused due to setup time violations
I tried simulations in Xilinx ISE and got output as o/p2 in the image.
I am attaching this image to illustrate my problem.
Dear Pranto
Hi
They are correct but one of the out puts is inverted instead of the other one . see your inverted waveform ( end of your page , right section ) this section has problem .
Best Wishes
Goldsmith
Dear Pranto
Hi
They are correct but one of the out puts is inverted instead of the other one . see your inverted waveform ( end of your page , right section ) this section has problem .
Best Wishes
Goldsmith
- - - Updated - - -
Dear Pranto
Hi
They are correct but one of the out puts is inverted instead of the other one . see your inverted waveform ( end of your page , right section ) this section has problem .
Best Wishes
Goldsmith
The result from such a simulation is not very interesting. The important thing here is that the real circuit will be unpredictable if you violate the setup/hold timing.
You can get the first or the second result, or the problematic metastable behavior.
There are circuits which have signals synchronous with clock signal. The main question I had was regarding such a circuit where
the signals are generated on the clock edge. For simplification I regarded the ckt as a D flip flop.
Based on my understanding the o/p1 is more probable case due to setup time requirements and nearly zero hold time requirement
in modern circuits.But I dont have any concrete source for it.