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confusion regarding dielectric material used in vlsi fab..

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a_shirwaikar

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"When reducing the gate length of an MOS transistor, the depletion regions around the source and drain have also to be reduced, to avoid effects such as charge sharing and punchthrough. To scale down the depletion regions, the doping oncentration of the substrate can be increased and the biases applied (i.e. the supply voltage) can be reduced.
The increase in the substrate doping also increases the threshold voltage, and this makes it more difficult to turn on the device. To compensate for this the gate oxide thickness is reduced."

- i read this in another thread and i agree with it. but high - k dielectrics are a newer technology and hopefully a solution to the large amount of gate leakage due to the very thin SiO2 layer (order of a layer of atoms).

my doubt is this - wont using high - k dielectrics increase the threshold again and also cause subthreshold conduction to dominate once again??
i'm aware that it is recommended to use metal gate/high - k dielectric combination.. but does the metal gate's increased mobility overcome the increase in threshold of the device?

also, does anyone have a link from which i can download the book on low power methodologies by Keating?

thanks!
 

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