Confusion! Keyword:Layout/Virtuoso/LVS

[sophiefans]

I drew a schematic&layout according to a bandgap circuit. When LVS,the BJT number mismatched.
Because the BJT which the parameter "multiplier" was setted "8 " in schematic was recognized as "1" BJT in the netlist,while the "8" BJTs in layout was recongnized as "8".

How could i deal with it?
need your help
3X

 

[aomeen]

If the multiplyer of the model is not operating, the only solution is to connect 8 transistors in parallel, each with multiplier equal to 1...

 

[DenisMark]

LVS rules must have rule for sum parallel instance in one. In this case LVS wil not get u mistake. And Netlists for schematic and layout (how u describe) is right.

 

[jcpu]

Dear sophiefans:

When mutiple parallel BJT are connected together,
they often get reduced to one big BJT.
It is really the "total Emitter Area" (AE) that LVS software checked,
but command files have to properly initiate this AE checking function.

Have fun,

 

[sunny0421]

i think the case is just like thansistors(parallel connection),lvs file only check the total size,you should make 8 bjt as a big one in layout side,but i 'm not quite sure

 

[YESH_23]

the lvs rule dec was unable to reduce the parally commected bjt's just modify that..