Bryan79
Newbie level 5
pll lock range
I am a bit confused over these PLL terminologies.
This is what I get.
Lock range: Maximum initial frequency offset which PLL acquire lock without cycle slips (in a single beat between reference signal and feedback signal)
Pull in range: Maximum initial frequency offset which PLL eventually acquire lock but with cycle slips. It is the largest value of offset for which the loop can still lock/pull-in, even with many cycle slips. If offset greater than pull in range, then the loop cannot acquire lock.
Pull out range: The pull-out range is that frequency step which causes a PLL to fall out lock if applied to the reference input of the PLL. The PLL may acquire lock again through a slow pull-in process.
Hold range: When PLL is phase-locked, it is the maximum frequency range in which frequency of the input reference signal can slowly be pulled away from the free running frequency of VCO but PLL still maintain phase-locked condition. It is static stability limit.
lock range < pull out range < pull in range < hold range
Question:
1. What happens if the reference signal offset frequency exceed lock range, but smaller than pull out range?
2. Any idea how to simulate the above terms, given I have formulas to calculate each of them?
Thanks.
Added after 5 hours 31 minutes:
I think I have found a very good document that explains these 4 terms (at pg 7,8)
PLL presentaton by Texas Instrument:
http://pasquale.lamanna.tripod.com/sitebuildercontent/sitebuilderfiles/file.pdf
I am a bit confused over these PLL terminologies.
This is what I get.
Lock range: Maximum initial frequency offset which PLL acquire lock without cycle slips (in a single beat between reference signal and feedback signal)
Pull in range: Maximum initial frequency offset which PLL eventually acquire lock but with cycle slips. It is the largest value of offset for which the loop can still lock/pull-in, even with many cycle slips. If offset greater than pull in range, then the loop cannot acquire lock.
Pull out range: The pull-out range is that frequency step which causes a PLL to fall out lock if applied to the reference input of the PLL. The PLL may acquire lock again through a slow pull-in process.
Hold range: When PLL is phase-locked, it is the maximum frequency range in which frequency of the input reference signal can slowly be pulled away from the free running frequency of VCO but PLL still maintain phase-locked condition. It is static stability limit.
lock range < pull out range < pull in range < hold range
Question:
1. What happens if the reference signal offset frequency exceed lock range, but smaller than pull out range?
2. Any idea how to simulate the above terms, given I have formulas to calculate each of them?
Thanks.
Added after 5 hours 31 minutes:
I think I have found a very good document that explains these 4 terms (at pg 7,8)
PLL presentaton by Texas Instrument:
http://pasquale.lamanna.tripod.com/sitebuildercontent/sitebuilderfiles/file.pdf