I use conformal to compare logic with netlist and RTL. But some logic is synthesized by retiming. Can I set some constraints to compare retiming netlist and RTL? And is set Black-box means just compare the input and output logic of the Black-box?
Here's the answer from my training materials.
Although I've not got time to go through it : )
For simple pipeline retiming circuit,
1. pipeline retimed module must be root module
2. can use "add module attribute <module> -pipeline_retime [-dff2buffer] [-golden|-revised]"
For advanced pipeline retiming,
you need Conformal Ultra license.
read library
read design
.....
add module attribute xxxx -pipeline_retime
set system mode lec
analyze datapath -merge
add compare point -all
compare
oh, I dont think root module means top module.
Root module should be current target module to be compared.
The current module could be the top design or a sub-moudle inside.
There's a command "set root module xxx " in LEC.
For it's a simple retimed without Ultra license,
I guess, the tool could not handle the retiming comparation through design hierarchy boundary.