Conformal Asic LEC problems

[leongch]

change names lec

Hi,

I am cleaning my design files using the HAL tools, and it requires us to change the signal to CAPITAL letter instead of lower case.
After I change the signal name, in the LEC it give me warning as there's no common key points as the name of the signal has changed.

May I knw in the Conformal Asic tool, any setting can be done to let the conformal tool know the changed of name of the signal is actually the same as the golden design?

Thanks...

 

[aji_vlsi]

cadence conformal-asic

Hi,

I am cleaning my design files using the HAL tools, and it requires us to change the signal to CAPITAL letter instead of lower case.
After I change the signal name, in the LEC it give me warning as there's no common key points as the name of the signal has changed.

May I knw in the Conformal Asic tool, any setting can be done to let the conformal tool know the changed of name of the signal is actually the same as the golden design?

Thanks...

I'm surprised that you changed your signal names due to a poor LINT report. All the lint tools I've used had several ways to handle it:

--> Either turn off that check
--> Rewrite the rule to accept it as is.

Also which HDL do you use? I guess Verilog (as VHDL is CaseInSensitive anyway ).

I recommend that you look at HAL doc and fix that lint error than changing the code.

On a side note - a mere name change doesn't usually confuse a good tool like COnformal, there must be some thing else that's going wrong, if possible I suggest you create a simple testcase and send to Cadence support.

Regards
Ajeetha, CVC
www.noveldv.com

 

[leongch]

what is lec in asic

yeah ... I know some of it is very stupid warning but my manager want emphasis to have 0 warning from HAL in the design.

I know at LINT/HAL tool we can set it as -NO check just the team manager refuse to use it.
So I have to find ways to fix the problems at LEC

 

[cdic]

lec issues asic design

yeah ... I know some of it is very stupid warning but my manager want emphasis to have 0 warning from HAL in the design.

I know at LINT/HAL tool we can set it as -NO check just the team manager refuse to use it.
So I have to find ways to fix the problems at LEC

, it's always happening, stupid manager/leader produce stupid problem and dump them to the poor team member.
Go back to your problem, LEC should be able to recoganize the new design without any problem if there are only only name changes, so there must something else get changed, maybe your design(netlist or RTL) is case sensitive before changing the name?

 

[no_mad]

conformal-asic

hi,

Correct me if I'm wrong.
Usually, lint check is not in ASIC/FPGA design flow.
This is just an optional requirement.

For example, if the designer practice good coding style in their design, there is no need to have lint check.

What do you guys think?

I had this argument with my proj leader. He wants to add lint check in our ASIC flow. Thus, I gave him my explanation as mention above.

He has the same ideas as leongch's manager, which is 0 WARNING from HAL in the design.

Thanks in advance.