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Configuring JESD parameters in Xilinx JESD204 IP

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samg

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I am more of a beginner and I am trying to understand how to configure and use the Xilinx JESD204IP. Currently, I am using Vivado v2012.4 and the target is to interface a kintex 7 FPGA with an ADC that supports JESD204B. I am going through the example design and certain things don’t make sense to me.

1. For the module “i_jesd204_v3_1_0”, the output (rxdataout[31:0]) seems to be a shifted version of the input (rxdata[31:0]). It is shifted by 17 cycles to be exact, along with the rx_start_of_frame and rx_end_of_frame signals. Then what is the functionality of the “i_jesd204_v3_1_0” block??

2. Also, the top level test-bench configures only three parameters with the “axi_write” function. But the address used does not concur with the address mentioned for the parameters in the product guide. Eg. For setting the F parameter , the test-bench in example design uses an address of x010 whereas product guide mentions the address as x020. Then how to configure the other JESD parameters??

Am I missing something here??
 

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