configuration of spartan problem

[amin]

xilinx prom configuration spartan

hello
I have problem in configuration of spartan XCS10PC84 with jtag and foundation 3.3ISE.
I pulldown INIT in powerup and then using jtag programer to program device.
but after massage the program is done, DONE pin remain low.
I read many document in Xilinx support site but cann't solve this.
Any idea, please

 

[knavekid]

I'm talking from memory here...

It seems to me that I had to change some properties in generating the BIT file in order to program the device via JTAG. The BIT file for jtag programming is different than the BIT file for loading from a configuration PROM.

I chose to avoid the hassle and simply program the 18CV512 configuration PROM every time I make a change. I haven't programmed the XCS40 in this design directly via jtag since early hardware debug.

Also, check out the Xilinx answers database.

I hope this helps.

 

[amin]

thanks for reply
I read in answer record that for jtag programing I should change option the startup clock in Bitgen options and set to the JTAG clock as opposed to CCLK (which is used for the master/slave configuration modes).
but options are CCLK and User clock.
What is the problem?