configurable block rom using vhdl

[rali]

generic rom vhdl code

hi,
i want to implement a block rom with generic read width and read depth in vhdl.i'm using modelsim se.Can xilinx core gen block rom be used to have the generic read width and depth or should a vhdl code be written to infer block rom.The design is to be synthesized in xilnx virtex 2 fpga.

 

[haneet]

rom using vhdl coding

I guess it should work.
I have used the core gen blocks but they were for Verilog files and didnt face any issues...

Haneet

 

[Tan]

rom in vhdl

I have used the coregen blocks..They work well.But not generic.You have to specify breadth and width in the coregen and genarate.
Instantiate the generated block.

 

[rali]

vhdl using generate

thanks for the replies.
i too thought the core gen blocks need the width and depth fixed.So to have a generic rom i'll have to write a vhdl code for the rom? could anyone please guide me how to infer block rom.

 

[shanmugaveld]

infer rom in xilinx

After generating RAM with fixed width and depth I used to create different depth using "generate" function in VHDL.
Using generate statement u can vary the depth of the RAM.

 

[Tan]

vhdl rom

but generate function is not synthesizable i guess..

 

[rali]

vhdl generate statement ram

thanks very much guys for your help.i'm not using xilinx core gen.i'm writing the vhdl code for the rom for now.

 

[Tan]

vhdl rom using generate

thanks very much guys for your help.i'm not using xilinx core gen.i'm writing the vhdl code for the rom for now.

It will occupy extra hardware if you write the code.may I know why you are not interested to use the coregen?

 

[rali]

rom en vhdl

i wanted to have a reconfigurable rom, the read width and depth may be non standard sizes and are required to be changed so that the component using the rom can be tested for performance using different wordlengths.
actually there are many sizes of arrays to be read depending on the configuration,3x3,5x5,9x9 and so on.the individual array element sizes and the array sizes are to be varied for the testing.i thought having a configurable xilinx core gen block rom and having different mif files for the cases might be the solution.maybe someone can suggest a better solution.for now i'm concentrating on the other blocks in the design and thought i can come back to the rom later.for now i'm using a case statement.if the xilinx core is used can the read widths be any size? in one location the rom stores one 2D array (9 for 3x3,81 for 9x9,..)so the read width will change depending on the element size...similarly the read depth will also change depending on a configuration value.
if anyone has suggestions on how this can be done pl help.

 

[shanmugaveld]

vhdl generate block

Hi TAN,

Generate statement is synthesizable...