Conductor intruding into multiple dielectric layers in ADS

[SawabyPlus]

I am modeling transmission lines on ADS. Conductors in the technology I am using (CMOS) intrude into two or more dielectric layers similar to the sketch below. ADS 2011.01 does not allow conductor thickness to be equal to or larger than layer thickness. Does anyone know some workaround?
I thought of a couple of things, would the solution be valid if I use vias to draw conductor lines? or, is there a way to calculate the average permittivity of the layers that this conductor pass through? (there are some other layers for other conductors)

 

[BigBoss]

You have to use Vias to connect these connector.

 

[SawabyPlus]

You have to use Vias to connect these connector.

Sorry, but could you elaborate more?
I have one horizontal conductor with a cross section that lies in different dielectrics. I cannot draw define a conductor as such in the ADS.

 

[BigBoss]

Sorry, but could you elaborate more?
I have one horizontal conductor with a cross section that lies in different dielectrics. I cannot draw define a conductor as such in the ADS.

Like this..

 

[kspalla]

You need to refine the modeling on dielectrics.
let say top dielectric is 30 mil and you have conductor passing 15 mil thick then better make two dielectric materials, bottom one with via and top dielectric matrial having no via.
like this approximation, though momentum is 2.5D but can be made more use of 3D modeling.
Using this method, I did modeling of two PCB substrates sandwich with sphere balls.
I simulated the signal flow from bottom pcb to top PCB through this ball bonding structure.

Regards

 

[RealAEL]

With 3 different dielectrics you need to define and map layers to each separately so you will need 3 copies of each shape.



Map one layer as a thick conductor strip intruded above the interface up into the Er1 substrate. The second as a via through Er2 substrate. Finally the third would be another thick conductor strip intruded below the interface down into the Er3 sunbstrate. It would look something like this:

 

[kspalla]

If the requirement is to connect top and bottom layers of Er2 then I agree with RealAEL.
but let assume the requirement is to connect dielectric loaded wave guide then model needs min 5 layers in my view.
Regards,

 

[SawabyPlus]

thnx all for the help!

I will try it RealAEL's way. I was concerned that ADS would treat vias different from conductors (vias allow only vertical currents maybe?)